By K C A Smith; R E Alley
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3-24) T ) From the result illustrated in Figure 3-15, we see that just like in the flash analysis, each technology becomes better than its predecessor only after a certain frequency boundary. However, the data in Figure 3-15 corrects the first order result that power should scale as 1/VDD. Depending on the speed requirements, technologies with lower VDD may yield lower power. 4 Slewing In the above discussion, we have assumed that the amplifier settles in a purely linear fashion. However, in practical switched capacitor circuits, the total settling time consists of a slewing and a linear settling time component.
Increasing design expertise is an important factor in progress, but it is virtually impossible to capture. Nevertheless, the results above provide good qualitative insight into the scaling behavior of matching-limited circuits and help explain the trends of the past decade. 5. SCALING IMPACT ON NOISE-LIMITED CIRCUITS In high-resolution ADCs, the power consumption tends to be set by noise constraints rather than matching. In cases where matching is critical, the desired accuracy is usually achieved through some form of calibration.
Device physics shows that the decrease in intrinsic gain is due to increased channel length modulation and Drain Induced Barrier Lowering (DIBL) for shorter channels . Figure 3-5 shows intrinsic gain for the different technologies and drain bias for VOV=200mV. 18µm case is the extremely gentle transition to acceptable gain levels. 6V is required to achieve a device gain of 20. 8V. Figure 3-6 shows a zoom into the realistic biasing range that can be allocated in today’s designs. Just like decreasing VDD, the low intrinsic device gain in short channel technologies can be regarded as a dynamic range penalty.
Electrical circuit theory by K C A Smith; R E Alley